1. Field of the Invention
This invention relates to a sampling clock reproducing circuit for reproducing data sampling clock signals, which is used in a teletext receiver for reading out the information (including character and picture data and to be hereinafter called the teletext signal) superposed on the television signals in a predetermined horizontal scanning period.
2. Description of the Prior Art
The character data signals in the teletext broadcast system are binary NRZ signals of a data packet form in one horizontal scanning period (1H) and superposed on one to several desired Hs in the vertical blanking period of video signal.
FIG. 1 is a wave form chart exemplary of a superposed character data signal (the data packet), in which the character data signal comprise header and information data, the header including clock-run-in signal framing code signal and data discrimination code signal, the clock-run-in signal being the synchronizing signal for reproducing the data sampling clock signal (to be hereinafter abbreviated to the sampling clock), the framing code signal being for synchronizing the data packet.
Now, in the teletext broadcast system, the character signal in FIG. 1 is transmitted and then reproduced at the receiving side. The receiving side needs reproduce the sampling clock accurately for sampling the subsequent signals on the basis of clock-run-in signal. The frequency of sampling clock is different in the system of every country, but equal to two times the fundamental frequency of clock-run-in signal, which is prescribed in Japan to 5.73 MHz (=364 f.sub.H =(3/5).multidot.f.sub.sc, where f.sub.H : frequency of horizontal synchronizing pulse, f.sub.sc : frequency of chrominance subcarrier. The Japanese system will be described below.
It is necessary for reproduction of sampling clock to set the frequency to 5.73 MHz and simultaneously coincide the phase with the clock-run-in signal. Since the jitter in the sampling clock, when the SN ratio of the input signal deteriorates, has a large influence on the reproduction of the input data, the jitter should be restricted even when the SN ratio deteriorates.
An example of conventional sampling clock reproducing circuit used for solving the above problems will be described below.
The teletext signal in the vicinity ofthe clock-run-in signal is sampled through a band-pass filter of 2.86 MHz and a gate circuit and doubled, and thereafter passes through a band-pass filter of 5.73 MHz, so that an output thereof drives a ringing oscillator to generate the preliminary sampling clock, which is used for framing code detection in order to synchronizing the frame. On the other hand, the main sampling clock divides the signal of frequency of n times 5.73 MHz (e.g. five times=28.6 MHz) into 1/n by a counter. The preliminary sampling clock samples the teletext signal, and the framing code obtained after error-correction resets the counter, thereby obtaining a proper sampling clock synchronized in phase. Such a conventional system is very complicated.
Since the high frequency of 28.6 MHz is divided during the oscillation at five times larger than 5.73 MHz, the high harmonic generated at that time gets in an antenna, so that in some cases the error rate largely increases with respect to the reception from a particular station. For example, while the 9th channel in Japan has the video carrier frequency of 199.25 MHz, the high harmonic of seven times 28.6 MHz is of 200.2 MHz, so that the beat signal of about 1 MHz is produced to largely affect the data reproduction.
The sampling clock, even when phase-synchronized with the clock-run-in signal, needs be phased through a phase-shift circuit corresponding to the circuit constitution of sampling clock reproduction system and to that of data slice system. Also, the teletext data signal, which is an intermittent signal for 1 to several Hs per one field, is defective in that its phasing is difficult to adjust.
Next, FIG. 11 is a circuit diagram exemplary of a conventional phase-comparison circuit, in which reference numerals 201 and 202 designate input terminals for signals A and B to be phase-compared, and 203 designates a phase difference detection circuit. Resistor 204 is a load resistor to the phase difference detection circuit 203, a transistor 205 is an emitter follower transistor to keep supply voltage to the load resistance 204 V.sub.2 -V.sub.BE (where V.sub.BE : voltage across the base and the emitter of transistor 205, of about 0.7 V). 206 designates an input terminal given gate pulse to turn on switches 207 and 208 for the phase difference detecting time period, the switches 207 and 208 operating in association with each other. Voltage variation at the node a for the period of turning on the switches 207 and 208 to detect a phase difference between the signals A and B is transmitted to a capacitor 211 through a transistor 209 and a resistor 210, a resistor 212 determining the base bias voltage of transistor 213, a resistor 214 determining a bias current for transistors 213 and 209, and 215 and 216 designate current sources respectively.
When switches 207 and 208 are off after phase detection, the base voltage of transistor 209 is V.sub.2 -V.sub.BE and that (V.sub.3) of transistor 213 is V.sub.1. In case that V.sub.2 -V.sub.BE is designed to be higher than the maximum voltage developed at capacitor 211, the transistor 209 is off and the transistor 213 also is of equal voltage (V.sub.1) across the base and emitter so as to be off. Hence, upon turning the switches 207 and 208 off, voltage of capacitor 211 is held, which is output as the phase difference detection voltage from the output terminal 217.
FIG. 12 shows the voltage relation between the FIG. 11 circuit and the FIG. 13 circuit to be discussed below. In FIG. 12, V.sub.a and V.sub.b are mean DC voltages at the nodes a and b respectively and e is a variation in phase difference detection voltage, the variations e at the nodes a and b being equal because the transistor 209, when on, operates as the emitter follower. The voltage difference between V.sub.b and V.sub.a is V.sub.BE (where V.sub.BE : voltage across the base and emitter of transistor 209). When a current flowing in the current source 215 is assumed 2 I.sub.1, the mean current of I.sub.1 flows in the load resistor 204 connected to one output at the phase difference detection circuit 203.
Accordingly, a resistance value of resistor 204 is represented by R.sub.1, V.sub.a is given by the following equation: EQU V.sub.a =V.sub.2 -V.sub.BE -I.sub.1 R.sub.1 ( 1)
In order to completely turn off the transistor 209 for the holding period as aforesaid, the variation at the node b should not be higher than V.sub.2 -V.sub.BE as shown by the dotted line in FIG. 12. Hence, the maximum value of variation of voltage at the node a becomes to be restricted by V.sub.2 -2V.sub.BE. In case of switching operation, the variation reaches the maximum value V.sub.2 -V.sub.BE so that voltage at the node b rises up to V.sub.2, but when the switches 207 and 208 are off, the base voltage at transistor 209 rises only to V.sub.2 -V.sub.BE, whereby the transistor 209 is not off and voltage of capacitor 211 drops to make it impossible to hold normal voltage. As a result, the dynamic range of phase comparison circuit should be restricted for use.